In a substrate having a wiring layer to which a plurality of vias are coupled, when current flows from the wiring layer to the vias, the current may crowd into a particular via, causing a break due to electromigration. Thus, a method for inhibiting current from crowding into a particular via has been suggested. One example is a method that inhibits current from crowding into the vias at both ends by making the electrical resistance of the wiring layer in the regions between the vias at both ends and the vias next to the vias at both ends greater than the electrical resistance in the remaining region as disclosed in for example, Japanese Patent Application Publication No. 2010-62530 (hereinafter, referred to as Patent Document 1).
In addition, there has been known a method that improves the supply capacity of the power source by making the thickness of a power supply layer or a ground layer provided to a printed circuit board greater than the thickness of a conductive circuit layer that is a signal line, as disclosed in, for example, Japanese Patent Application Publication No. 2005-167140 (hereinafter, referred to as Patent Document 2). There has been known a method that reduces the delay of power supply by making the pitch of a through-hole conductor located immediately below the region in which a semiconductor element is to be mounted less than the pitch of a through-hole conductor in other regions in the printed circuit board, as disclosed in, for example, Japanese Patent Application Publication No. 2007-180076 (referred to as Patent Document 3).